The instruction set architecture (ISA) of a microprocessor usually defines registers that correspond to entries in a register file and are used to stage data between various memory modules and functional modules of the microprocessor. Modern microprocessors may include a register bypass network that provides additional data paths to, for example, forward results that have not been committed or to eliminate data hazards in the pipelines. Some conventional microprocessor designs use a full bypass network such that a piece of data generated in a specific cycle from a register file write port becomes available at one or more register file read ports in the next cycle and thus may result in a reduced number of read-after-write stalls between instructions that write to a register and a subsequent instruction that reads the same register. Although a full bypass network may reduce the number of clock cycles when executing the same program, a full bypass network may exhibit several disadvantages when compared to a partial bypass network. Therefore, there exists a need for a method, system, and computer program product for implementing a microprocessor with a selective register file bypass network.